Improving Accuracy of Analog-to-Digital Converters

This paper introduces three popular analog-to-digital converter (ADC) architectures to readers: the flash ADC, the multi-step flash ADC, and the pipeline ADC. The fundamental operating principles of these three architectures are described. The specific topic of interest of this paper is methods of improving ADC accuracy. For the flash ADC, the concept of 2X interpolation to increase ADC resolution without significant area/power overhead is described. A design technique in reducing inter-channel mismatch for a time-interleaved multi-step flash ADC is then presented. Finally for the pipeline ADC architecture, a “passive capacitor mismatch error averaging” methodology is illustrated which relaxes capacitor matching requirement, reducing first order mismatch errors to second order.